1. Field of the Invention
The present invention relates to a semiconductor memory device, and, more particularly, to a dynamic random access memory (DRAM) that needs to periodically refresh stored data in memory cells. More specifically, the present invention relates to a construction for controlling the refresh of an embedded DRAM that is assembled in a system LSI (Large Scale Integrate Circuit).
2. Description of the Background Art
In the data processing field or the like, a system LSI, formed by integrating a logic such as a processor and a memory device on the same semiconductor chip, has been used in order to process data at a high speed with low power consumption. In this system LSI, since the logic and the memory device are interconnected to each other through on-chip interconnection lines, it is possible to provide at least the following advantages:
(1) Since the load of a signal line is small as compared with an on-board wiring line, it is possible to transmit data/signals at a high speed.
(2) Since there is no limitation of the number of pin terminals, the pitch of signal lines of the data bus is made as small as the memory internal interconnection lines, thereby making it possible to increase the number of data bits, and consequently to widen the band width of data transfer.
(3) In comparison with a construction in which discrete components are arranged on a board, it is possible to reduce the system scale and to achieve a compact small-size system since respective components integrated on the semiconductor chip, and
(4) Since a macro reserved as a library can be arranged for a component formed on the semiconductor chip, the designing efficiency is improved.
For the reasons as described above and others, the system LSI has been widely used in various fields. With respect to the memory device to be integrated, memories, such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory) and flash EEPROM (electrically programmable and erasable read only memory), have been used. Moreover, examples of the logic include a processor for carrying out controlling and processing operations, an analog processing circuit for carrying out an analog signal processing operation, such as analog/digital conversion and digital/analog conversion, and a logical circuit for carrying out logical processing such as specialized image processing.
Among semiconductor memory devices, the DRAM has a memory cell constituted by one capacitor and one transistor, and consequently is small in area occupied by the memory cell, thereby making it possible to achieve a large storage capacity with a small occupied area. However, information is stored in the capacitor of a memory cell in the form of charges. Consequently, the charges stored in this capacitor of a memory cell might be lost to cause the stored data to lose due to a leakage current, such as a junction leakage current between the substrate area and the impurity area of the storage node, a channel leakage current of the memory cell transistor, and a leakage current of the capacitor insulating film. In order to prevent the data loss due to such leakage currents, a refreshing operation for re-writing or restoring memory cell data at predetermined cycles is carried out.
In this refreshing operation, the refreshing is carried out at predetermined time intervals such that, within a maximum refresh time tREFmax determined by a memory cell having the shortest data holding time in the semiconductor chip, the refreshing operation is completed once on all the memory cells in the memory array.
With respect to this refreshing operation, during the normal operation mode for making data accesses to the DRAM, an external logic or an external controller issues a refresh instruction so that refreshing is carried out in the DRAM. Therefore, the refresh instruction needs to be issued every predetermined refresh interval in order to carry out this refreshing in the DRAM, and an access to the DRAM being refreshed needs to be suspended until the refresh cycle of the DRAM is completed. Thus, a complicated controlling and managing process on the memory is required.
In the case of the SRAM, the memory cell is constituted of a flip-flop circuit so that different from the DRAM, no refreshing operation is required. Therefore, in mobile information terminals or the like for which down-sizing is strongly demanded, the system construction using the SRAM that eliminates such a complicated memory controlling and managing process related to refreshing as described above has been widely used, in order to simplify the system construction.
However, in recent years, the mobile information terminal has been greatly improved in function so as to deal with image information as well, and has come to require a memory function with a large storage capacity. The SRAM has a construction in which one memory cell is constituted by four transistors and two load elements, and consequently has a memory cell size of nearly ten times as great as the memory cell size of the DRAM. Therefore, in the case when the SRAM is used for a memory with a large storage capacity, such problems arise that the chip area increases to be unable to satisfy the request for down-sizing, and the chip cost increases greatly, resulting in an increased cost of mobile information terminals.
Therefore, there has been a strong expectation for the DRAM that can achieve a memory with a large storage capacity at a low cost with a small occupied area, as a substitute for the SRAM. However, as described above, the DRAM requires a complex memory controlling operation related to refreshing and the existing DRAM is not compatible with the SRAM, and therefore, it is not easy to adopt the DRAM as a substitute memory for the SRAM.
It is an object of the present invention to provide a fully hidden refresh DRAM which can completely hide the refreshing operation from outside.
Another object of the present invention is to provide a DRAM having an interface that is compatible with the SRAM.
Still another object of the present invention is to provide a DRAM suitable for installation in a system LSI and easy in memory control.
The semiconductor memory device in accordance with the present invention includes: a plurality of memory sub-blocks each having a plurality of memory cells; a refresh instruction issuing circuit for issuing a refresh instruction for refreshing a memory cell; a refresh address generation circuit for generating a refresh address that specifies a memory cell to be refreshed in each memory sub-block; and a refresh control circuit arranged corresponding to each memory sub-block, and for, upon receipt of the refresh instruction, permitting an execution of refreshing operation on a corresponding memory sub-block in accordance with a received refresh address when the corresponding memory sub-block satisfies a condition different from a predetermined condition.
Upon issuing the refresh instruction, the refresh instruction is commonly issued to the memory sub-blocks inside the memory, and the refreshing operation is executed on a memory sub-block arranged in a specific condition. Therefore, an external memory controller such as a logic is not required to carry out a refreshing operation at all. Thus, it is possible to completely hide the refreshing operation in this semiconductor memory device from outside. Consequently, it becomes possible to achieve a substituting memory for the SRAM, which can be accessed in the same manner as the SRAM.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.